(1) Field of the Invention
This invention relates to a cache memory device, a semiconductor integrated circuit, and a cache control method and, more particularly, to a cache memory device with a memory data protection function based on a parity function or an error checking and correcting (ECC) function, a semiconductor integrated circuit, and a cache control method.
(2) Description of the Related Art
In computer systems which call for high reliability, various techniques for supporting high reliability are used for components, such as central processing units (CPUs), cache memories, main memories, and I/O devices.
With cache memories, for example, the correctness of their contents must be guaranteed to improve data reliability. An error detection method based on parity or an error detection and correction method based on ECC is used for guaranteeing the correctness of the contents of cache memories.
An example of a conventional cache memory device is given below.
FIG. 7 shows the structure of an example of a conventional cache memory device in which an ECC function is used for data random access memories (RAMs).
In this example, a cache memory device 800a includes n ways (storage blocks) WAY0, WAY1, . . . , and WAY(n-1). An address used when a CPU (not shown) accesses a main memory (not shown) is also shown. The cache memory device 800a includes n tag RAMs 801-1, 801-2, . . . , and 801-n, n comparators 802-1, 802-2, . . . , and 802-n, n data RAMs 803-1, 803-2 . . . and 803-n, n ECC code sections 804-1, 804-2, . . . , and 804-n, selectors 805 and 806 for selecting a way in accordance with a way selection signal, and an error detection and correction section 807.
The tag RAMs 801-1 through 801-n each store tag information. The tag information is designated by a low order bit address (index address) of an address specified by the CPU (not shown) and is read out. Tag information outputted from the tag RAMs 801-1 through 801-n by using the same index address differs among the ways.
The comparators 802-1 through 802-n respectively compare a high order bit address (tag address) of the address specified by the CPU (not shown) and the tag information read out from the tag RAMs 801-1 through 801-n, and output a way selection signal for selecting a way in which they match.
The data RAMs 803-1 through 803-n store part of data stored in, for example, the main memory (not shown) and output data specified by the index address.
The ECC code sections 804-1 through 804-n store ECC codes corresponding to the data stored in the data RAMs 803-1 through 803-n, respectively, and output ECC codes specified by the index address.
In accordance with the way selection signal, the selector 805 selects and outputs data read out from one of the data RAMs 803-1 through 803-n included in the way selected.
In accordance with the way selection signal, the selector 806 selects and outputs an ECC code read out from one of the ECC code sections 804-1 through 804-n included in the way selected.
By using the ECC code, the error detection and correction section 807 detects a 1- or 2-bit error and corrects the 1-bit error.
The operation of the conventional cache memory device 800a will now be described.
When the CPU (not shown) accesses the main memory (not shown), the tag information specified by the index address is read out from the tag RAMs 801-1 through 801-n. The comparators 802-1 through 802-n respectively compare the tag address and the tag information read out from the tag RAMs 801-1 through 801-n, and output the way selection signal for selecting the way in which they match.
On the other hand, the data specified by the index address is read out from the data RAMs 803-1 through 803-n. Similarly, the ECC codes specified by the index address are read out from the ECC code sections 804-1 through 804-n. The selector 805 selects the data read from one of the data RAMs 803-1 through 803-n included in the way specified by the way selection signal and inputs it to the error detection and correction section 807. The selector 806 selects the ECC code read out from one of the ECC code sections 804-1 through 804-n included in the way specified by the way selection signal and inputs it to the error detection and correction section 807.
It is assumed that the tag information stored in the way WAY0 matches the tag address inputted as a result of comparisons made by the comparators 802-1 through 802-n. Then the selector 805 selects the data stored in the data RAM 803-1 in the way WAY0 and the selector 806 selects the ECC code stored in the ECC code section 804-1 in the way WAY0. The selected data and ECC code are inputted to the error detection and correction section 807.
By using the data inputted and the corresponding ECC code, the error detection and correction section 807 then detects a 1- or 2-bit data error, corrects the 1-bit data error, and outputs the data.
As stated above, with the conventional cache memory device 800a the ECC codes stored in the ECC code sections 804-1 through 804-n are used for detecting and correcting an error. By doing so, high reliability is actualized. The case where ECC codes are used has been described. However, the major part of the above description applies to the case where a parity function is used. A cache memory device includes an area where parity check bits corresponding to data stored are held, and an error is detected by using a parity check bit.
By the way, memory data protection using a parity function or an ECC function is unnecessary to some uses for a system. In such cases, manufacturing cache memory devices without a memory data protection function and cache memory devices with a memory data protection function causes the problem of delivery time or costs. Accordingly, a technique for nullifying a memory data protection function included in a cache memory device by, for example, a control signal at the time of not using it is proposed (see, for example, Japanese Patent Laid-Open Publication No. Sho64-78498 or No. Hei1-223700).
FIG. 8 shows a conventional cache memory device in which a memory data protection function can be nullified.
Components that are the same as those shown in FIG. 7 are marked with the same symbols and descriptions of them will be omitted.
A cache memory device 800b includes a selector 808 for selecting output from a selector 805 or output from an error detection and correction section 807 in accordance with a mode selection signal.
To nullify an ECC function of the cache memory device 800b, a mode selection signal is used for making the selector 808 select and output output from the selector 805. To use the ECC function of the cache memory device 800b, a mode selection signal is used for making the selector 808 select and output an error correction result outputted from the error detection and correction section 807.
However, if a memory data protection function based on a parity function or an ECC function is nullified, then data stored in an area for storing parity check bits or ECC codes is not used. As a result, the storage area where the data is held will waste.